1. Field of the Invention
The present invention relates to an input switching device used in a logic MOS integrated circuit.
2. Description of the Related Art
A conventional input switching device comprises a register, a first and second logic circuits, and a first and second flag circuits. The register receives an arbitrary input signal and then stores it. The first logic circuit is supplied with the input signal and data stored in the register. The first logic circuit is controlled in accordance with the condition of a flag of the first flag circuit and outputs one of the input signal and the data stored in the register. The second logic circuit is supplied with an input signal from an input pad of an integrated circuit. The second logic circuit supplies the input signal from the input pad to a clock input terminal of the register in accordance with the condition of a flag of the second flag circuit to thereby control the operation of the register or supplies the input signal from the input pad to peripheral circuit as an input signal. In other words, the input signal supplied from the input pad is selectively used as a clock signal for controlling the operation of the register and an input signal of the peripheral circuit. This circuit arrangement aims at reducing the number of IC pads by using the input pad for both inputting clock signals and inputting signals to the peripheral circuit.
The first logic circuit comprises a first and second AND gates and a OR gate. The above-described arbitrary input signal is supplied to one input terminal of the first AND gate, and an output signal of the register is supplied to one input terminal of the second AND gate. An inverted signal of an output signal of the first flag circuit is supplied to the other input terminal of the first AND gate, and an output signal of the first flag circuit is supplied to the other input terminal of the second AND gate. Output signals of the first and second AND gates are supplied to an OR gate, and the arbitrary input signal or the data stored in the register is output from an output terminal of the OR gate in accordance with the flag of the first flag circuit.
The second logic circuit comprises a third and fourth AND gates. An output signal of the second flag circuit is supplied to one input terminal of the third AND gate and its inverted signal is supplied to the other input terminal of the fourth AND gate. Input signals are supplied from the input pads to the other input terminals of the third and fourth AND gates. An output signal of the third AND gate is supplied to the clock input terminal of the register, and an output signal of the fourth AND gate is supplied to the peripheral circuit as an input signal.
With the above circuit arrangement, however, when the flag of the first flag circuit is set in the condition that the first logic circuit selects and outputs the data stored in the register, if the flag of the second flag circuit is set in the condition that the second logic circuit supplies an input signal to the peripheral circuit, any clock signal is not supplied to the register and thus a malfunction may occur. In order to select the data stored in the register and output it therefrom, a clock signal needs to be supplied to the register and, in other words, the register needs to be in an operating state. If the flag of the second flag circuit is set in the condition that an input signal from the input pad is supplied as an input signal of the peripheral circuit, the register is not operated since it does not receive any clock signal for control. It cannot be therefore thought that the data stored in the register is normally supplied to the first logic circuit and output therefrom. This attributes to the fact that the flags of the first and second flag circuits are set separately.
When the flag of the first flag circuit is set in the condition that the first logic circuit selects the arbitrary input signal, if the flag of the second flag circuit is set in the condition that the second logic circuit outputs an input signal as clock signal of the register, no problems occur in the circuit operation. However, since a clock signal is always input to an unused register, power consumption is wasted.
Since the flags of both the first and second flag circuits need to be set, the flag setting operation is complicated and a pattern for two flag circuits is needed within the IC, resulting in an increase in the are of the pattern.